1. Technical Field
The present invention relates in general to a method and system for sending large numbers of CMOS control signals into a separate quiet analog power domain and, in particular, to a method and system for sending large numbers of CMOS control signals into a separate quiet analog power domain on the same chip without detrimental noise transmission into the quiet power domain.
2. Description of the Related Art
In mixed signal designs having large amounts of CMOS logic, generally any CMOS control signals that need to connect and feed to circuitry in a quiet analog power domain are converted to low level differential signals before being used therein. Furthermore, any switching CMOS circuitry in the analog power domain must be kept to a minimum and somewhat isolated so that switching noise is not introduced onto the quiet analog power supply. Another concern in these mixed signal designs is the transmission of noise on the noisy logic power supply to the quiet power supply.
Problems occur for these designs when a large number, such as one hundred (100) or more, CMOS control signals need to be used in the analog power domain. Converting such a large number of signals to differential signals in the traditional way while also maintaining a small chip size is not at all practical. For example, such a conversion would require as many CMOS switching circuits in the analog power domain as signals to be converted, thus introducing a large amount of switching noise to the quiet analog power domain.
With reference now to the figures and in particular with reference to FIG. 1, a traditional or conventional prior art CMOS conversion multiplexer 10 that is used for converting CMOS signals to differential signals is shown. The CMOS conversion multiplexer 10 comprises various bipolar transistors 12, various field effect transistors (FETs) 14, a CMOS inverter 16, constant current sources 18, and various resistors 20 coupled together in the manner shown in FIG. 1. A power supply voltage VDD1 24 is applied to the multiplexer 10, and the multiplexer 10 is grounded at GND1 25 for proper operation of the multiplexer.
The general operations of multiplexer 10 is described as follows: The CMOS signal is sent into the multiplexer 10 at CMOS input signal 15. A CMOS signal is defined as a signal whose low level is 0V and its high level is the power supply. The signal A2 is in the analog part of the domain. If A2 is high, then the CMOS signal turns on the transistor Q9 and the collector of Q9 is pulled low. If A2 is low, then the CMOS signal turns on the transistor Q10 and the collector of Q10 is pulled low. Transistors Q9 and Q10 are a current steering differential pair meaning that the current through the current source is constant and either goes through Q9 or Q10 depending on the value of A2. The base of Q9 is either driven to the voltage value of VDD1 when it is on or is clamped by Q3 to 1 diode below VDD1 when it is off. Meanwhile, the base of Q10 is connected to a voltage divider whereas the base is held to a constant voltage that is a 1/2 diode below VDD1. The generally noisy input signal 15 is converted to low voltage level differential signals by the converter portion 10A of the circuit. Low level differential or ECL signals can be defined as two signals whose amplitude is small, for example 300 mV, and whose phase relationship is such that one is at its low voltage while the other is at its high voltage. This phase relationship is sometimes called 180 degrees out of phase. The outputs of the converter circuit 10A are used as inputs to the differential multiplexer 10B called MA and MB. When MB is high the ECL inputs B0 and B1 are transferred to the ECL Differential Outputs and when MA is high the ECL inputs A0 and A1 are transferred to the ECL Differential Outputs. For example, this could be a method by which a designer could use a control loop to choose dynamically between two delays of differing values. A0, A1 is chosen by the multiplexer 10 when A2 is high, and B0, B1 is chosen by the multiplexer 10 when A2 is low. Thus, the CMOS conversion multiplexer 10 chooses between two values in a control loop.
One problem with conversion multiplexer 10 is that it requires accurate current sources 18 and careful layout. Another problem is that it requires the CMOS signal to be referenced in the quiet power supply by using at least one CMOS inverter. Furthermore, for processing a large amount of signals, a conversion multiplexer 10 would be required for each signal to be converted. The current mirrors required for that many circuits would require a large amount of chip area. Also, the conversion of CMOS signals to differential signals is performed in a multiplexer 10, which is able to be viewed as one, single stage of circuits, but it requires a large amount of area, careful control of current and would inject switching noise on the quiet power supply by means of the CMOS inverter 16. At least one CMOS inverter for each signal to be converted is required on the quiet power supply. The injection of noise onto the quiet power supply is a means by which, for example, an accurate delay could be undesirably modulated.
With reference now to the figures and in particular with reference to FIG. 2, another CMOS conversion multiplexer 11 is shown. The multiplexer 11 is used to attempt to accomplish the conversion of CMOS logic signals into differential signals. The multiplexer 11 further comprises various bipolar transistors 12, various FETs 14, a current source 18, and various resistors 20 coupled in the manner shown in FIG. 2. Parasitic capacitance 26 are shown to exist at the various areas in FIG. 2. Also, power supply voltage VDD1 24 is used to drive the multiplexer 11, and the multiplexer 11 is coupled to ground GND1 25 for proper operations of the multiplexer 11.
The general operations of the multiplexer 11 is described as follows: The current source 18 provides a constant accurate current source for the multiplexer. The CMOS input signal is sent in as the MB signal which is inputted to the PFET T0 while the complimentary CMOS input signal (180 degrees out of phase from the CMOS input signal) is sent in as the MA which is inputted to the PFET T1. As stated earlier, the MA and MB signals will be relatively noisy signals. The PFET T0 provides an A-Select signal while the PFET T1 provides a B-Select signal. The PFETs T0 and T1 are driven from 0 to VDD1 with what are considered CMOS control signals. The transistors 12 are driven by the ECL low level differential signals 28. However, parasitic capacitances exist from the gate to the drain and the gate to the source of the PFETs T0 and T1. Parasitic capacitances also exist from the base to the emitter and the base to the collector of the bipolar transistors Q4 and Q5. The parasitic capacitances provides paths to communicate noise from power supplies that have a lot of switching noise on them and logic power supplies. CMOS signals look like CMOS input signal 15 in FIG. 3. differential signals 28. However, parasitic capacitances exist from the gate to the drain and the gate to the source of the PFETs T0 and T1. Parasitic capacitances also exist from the base to the emitter and the base to the collector of the bipolar transistors Q4 and Q5. The parasitic capacitances provides paths to communicate noise from power supplies that have a lot of switching noise on them and logic power supplies. CMOS signals look like CMOS input signal 15 in FIG. 3.
If the CMOS input signal 15 is connected directly to converter inputs MB and MA, the noise that is coupled to the outputs P10, P11 was unacceptable even though the design was compact and simple. Also to prevent problems that could be caused by ground shift between the two power domains, the incoming CMOS signals should be referenced to the analog power supplies to ensure full switching of the PFET. This referencing can be done using the CMOS inverters 16, but it introduces switching noise onto the quiet analog power supply VDD1. Also, the conversion of CMOS signals to differential signals is performed in a multiplexer 11, which is able to be viewed as one, single stage of circuits. When the signal MB is low, the signals A0, A1 are selected and when the signal MA is low, the signals B0, B1 are selected. This circuit, for example, could also be used to choose between two delays of different values by means of a control loop. Another problem with this design is that noise from the CMOS signals would be transmitted to a sensitive net by means of the parasitic capacitances 26. This noise transmission would modulate the delay of the multiplexer and affect as in the previous example the value of the precise delays desired.
In multiplexer 11, modulation of the desired value an the output may be a result of noise 34 (i.e. see FIG. 3) from the CMOS input signal 15 or subsequent signals MA, MB therefrom modulating the voltage on sensitive circuit nets such as S1 and S2 and thereby modulating the delay of the multiplexer 11. Noise may also be introduced to the non-noisy analog power supply in both multiplexers 10 and 11 from injection noise caused by CMOS switching devices switching on and off in the circuits denoted by the number 16 that are necessary to avoid problems caused by possible ground shift between the CMOS logic power domain and quiet analog power domain. The detail explanation of such switching and noise is shown in drawing 38 of prior art FIG. 4 (i.e. noise on power supply exists). In this case, the noise may be caused by current turning on and off every time devices are switched on and off. For example, the desired type of circuit in a quiet power domain is constant current circuits 18 in FIGS. 1 and 2. The circuits 16 in FIGS. 1 and 2 draw current when the output is changing state. Otherwise, it does not draw current. If a significant number of these types of circuits exist on the quiet power supply, the voltage of that power supply drops when the current is on and the voltage of the power supply rises when the current is off. In FIG. 2, the noise from either source, the switching on and off of current, or the transmission of noise via parasitic capacitances varies the delay of the multiplexer 11. The noise is detrimental in most analog applications.
Previous designs either had too much noise gain from the input to the output, required too many CMOS switching circuits on the quiet power supply, or were too complicated and large to use for converting a large amount of CMOS control signals. Generally, noise is desired to be eliminated or attenuated as much as possible from the noisy signal (i.e. CMOS input or even MA and MB signals) so that it is eliminated or minimized in effect on the output of the multiplexer. Furthermore, regarding FIG. 2, if nothing is done about the ground shift between GND1 and the logic ground, then CMOS inverters need to be placed on the analog power supply. These CMOS inverters also introduce switch noise onto the quiet analog power supply.
It is therefore advantageous and desirable to convert the CMOS signals in a simpler way while attenuating the noise transmitted to the small signal and to the quiet power supply from the large swing signal and the noisy logic power supply. It is also advantageous and desirable to eliminate the requirement of converting the control signals to low level differential signals in a traditional way before using them in a quiet analog power domain. It is further advantageous and desirable to eliminate the requirement of CMOS level switching circuitry on the quiet power domain. It is still also advantageous and desirable to provide a mixed signal design with large amounts of CMOS logic that reduces the noise gain from the input of the CMOS signal to the output of the low level differential circuit over previous designs. It is still further advantageous and desirable to provide a mixed signal design with large amounts of CMOS logic that reduces noise transmission from the large swing signal over previous designs. It is still further advantageous and desirable to provide a mixed signal design with large amounts of CMOS logic that reduces the transmission of noise on the signal from the logic power supply when the signal is at a steady state high or low over previous designs. It is still also advantageous and desirable to provide a CMOS conversion circuit design that overcomes the problems of the prior art such as having too much noise gain from the input to the output, requiring too many CMOS switching circuits on the quiet power supply, or being too complicated and large to use for converting a large amount of CMOS control signals.
It is therefore one object of the present invention to convert the CMOS signals in a simpler way while attenuating the noise transmitted to the small signal and to the quiet power supply from the large swing signal and the noisy logic power supply.
It is another object of the present invention to eliminate the requirement of converting the control signals to low level differential signals in a traditional way before using them in a quiet analog power domain.
It is a further object of the present invention to eliminate the requirement of CMOS level switching circuitry on the quiet power domain.
It is still also an object of the present invention to provide a mixed signal design with large amounts of CMOS logic that reduces the noise gain from the input of the CMOS signal to the output of the low level differential circuit over previous designs.
It is still a further object of the present invention to provide a mixed signal design with large amounts of CMOS logic that reduces noise transmission from the large swing signal over previous designs.
It is still another object of the present invention to provide a mixed signal design with large amounts of CMOS logic that reduces the transmission of noise on the signal from the logic power supply when the signal is at a steady state high or low over previous designs.
It is still another object of the present invention to provide a CMOS conversion circuit design that overcomes the problems of the prior art such as having too much noise gain from the input to the output, requiring too many CMOS switching circuits on the quiet power supply, or being too complicated and large to use for converting a large amount of CMOS control signals.
The foregoing objects are achieved as is now described. A CMOS signal transmission system for sending a large amount of CMOS signals into a separate quiet analog power domain. Transmission system comprises a converter sub-system which provides at least another device stage through which noise in the CMOS signals must flow and be attenuated to provide converted CMOS signals and a multiplexer coupled to the converter wherein the multiplexer receives converted CMOS signals from the converter sub-system and also receives delayed path control signals. The converter comprises a constant current source for providing a high level voltage reference and a constant current, two complimentary pass gates, and two sets of components for providing paths to ground from the constant current source through the two complimentary pass gates. When CMOS input signal is high and Complimentary CMOS input signal is low, the pass gate comprising transistors T9 and T1 is on and transistors T8 and T0 are off and connection BSEL is pulled high turning on bipolar transistor Q9 allowing current to flow through Q9 and pulling net SB low and selecting inputs B0, B1 to be transferred to ECL Differential Outputs. Likewise, when CMOS input signal is low and Complimentary CMOS input signal is high, pass gate comprising transistors T8 and T0 is on, and transistors T9 and T1 are off, and connection ASEL is pulled high turning on bipolar transistor Q8 allowing current to flow through Q8 and pulling net SA low and selecting inputs A0, A1 to be transferred to ECL Differential Outputs.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.